Storage node process for deep trench-based DRAM
US5656535A · kind A · utility
31Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Mar 4, 1996 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Mar 4, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/973
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.