Radhika Srinivasan
14Patents
11h-index
38Co-inventors
64Inventor score
Filing activity: Feb 22, 1996 → Apr 30, 2003
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5827765A | Buried-strap formation in a dram trench capacitor | Electricity | 60 | Expired |
| US6140208A | Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications | Electricity | 45 | Expired |
| US5656535A | Storage node process for deep trench-based DRAM | Emerging Cross-Sectional Technologies | 31 | Expired |
| US6130145A | Insitu doped metal policide | Electricity | 29 | Expired |
| US5792685A | Three-dimensional device layout having a trench capacitor | Electricity | 27 | Expired |
| US5844266A | Buried strap formation in a DRAM trench capacitor | Electricity | 24 | Expired |
| US5893735A | Three-dimensional device layout with sub-groundrule features | Electricity | 21 | Expired |
| US5923971A | Reliable low resistance strap for trench storage DRAM cell using selective epitaxy | Electricity | 18 | Expired |
| US6153474A | Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate | Emerging Cross-Sectional Technologies | 17 | Expired |
| US6190955A | Fabrication of trench capacitors using disposable hard mask | Electricity | 15 | Expired |
| US6074903A | Method for forming electrical isolation for semiconductor devices | Electricity | 12 | Expired |
| US6348394B1 | Method and device for array threshold voltage control by trapped charge in trench isolation | Electricity | 4 | Expired |
| US6797582B2 | Vertical thermal nitride mask (anti-collar) and processing thereof | Electricity | 1 | Expired |
| US6333531A | Dopant control of semiconductor devices | Electricity | 1 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.