Method of packaging a semiconductor device with minimum bonding pad pitch and packaged device therefrom
US5684332A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1995 |
| Grant date | Nov 4, 1997 |
| Priority date | — |
| Expiry date | Dec 20, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package for a semiconductor die having a plurality of bonding pads about its periphery is provided. The package has a plastic molding encapsulating the semiconductor die. The package also has a plurality of conductive leads with leads having inner and outer portions, the inner portions encapsulated in the molding and arranged substantially in a plane and radially about the semiconductor die with ends displaced from and forming a rectangle with four corners about the die. A bonding wire extends from each of the bonding pads to one of the inner portions of the leads. Bonding wire loop heights of approximately 8 mils are made with a specially designed tip of a capillary tool. The package also has a pair of leads with inner portions at opposite corners of the rectangle, each of the inner portions connected to a pair of bonding wires from a pair of contiguous bonding pads on the die. This double wiring arrangement prevents wire sweep during the injection molding step. Bonding pad pitches of 4 mils or less on the semiconductor die are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.