Method of forming a shallow junction by diffusion from a silicon-based spacer
US5710054A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 1996 |
| Grant date | Jan 20, 1998 |
| Priority date | — |
| Expiry date | Aug 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/259
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a shallow junction in an IGFET is disclosed. The method includes forming a gate insulator on a semiconductor substrate of first conductivity type, forming a gate electrode on the gate insulator, forming a sidewall insulator on an edge of the gate electrode, forming a silicon-based spacer over the substrate such that the sidewall insulator separates and electrically isolates the spacer and the gate electrode, and diffusing a dopant of second conductivity type from the spacer into the substrate. The diffused dopant forms a shallow region of second conductivity type in the substrate, and a shallow junction is substantially laterally aligned with the edge of the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.