Method of forming a recessed interconnect structure

US5767012A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• H. Jim Fulford · Austin, US
• Basab Bandyopadhyay · Austin, US
• Robert Dawson · Austin, US
• Fred N. Hause · Austin, US
• Mark W. Michael · Cedar Park, US
• William S. Brennan · Austin, US

Key dates

• Filing date: Jun 5, 1996
• Grant date: Jun 16, 1998
• Expiry date: Jun 5, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, formi…