Method for forming semiconductor integrated circuit device having a capacitor
US5804479A · kind A · utility
46Cited by
2References
25Claims
0Family size
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Key dates
| Filing date | Aug 9, 1996 |
| Grant date | Sep 8, 1998 |
| Priority date | — |
| Expiry date | Aug 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
The etch-back amount of a silicon oxide film of a memory array which is a higher altitude portion is increased when etching back and flattening the silicon oxide film by arranging a first-layer wiring on a BPSG film covering an upper electrode of an information-storing capacitative element only in a peripheral circuit but not arranging it in the memory array. Thus, a DRAM having a stacked capacitor structure is obtained such that the level difference between the memory array and peripheral circuit is decreased, and the formation of wiring and connection holes are easy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.