Non-volatile semiconductor memory and method of manufacturing the same
US5824583A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 14, 1997 |
| Grant date | Oct 20, 1998 |
| Priority date | — |
| Expiry date | Oct 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/685
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a non-volatile semiconductor memory having non-volatile memory cells capable of electrically erasing and writing data. Each memory cell has a floating gate formed on the surface of the semiconductor substrate above the channel region, and a control gate. The floating gate partially covers the channel region. Each memory cell is thereby constructed of a parallel connection of a floating gate transistor and an enhancement type transistor. The floating gate transistor is displaced in one of the widthwise directions of the channel region, or partially covers only the central portion of the channel region in the widthwise direction thereof. A plurality of memory cells are connected in series to constitute a basic block. Adjacent basic blocks are separated by an enhancement type MOS transistor. In this memory, a memory cell (floating gate) and an enhancement type MOS transistor (gate) are formed in self alignment with each other using the same mask. In addition, in this memory, a control gate and a floating gate are formed in self alignment with each other using the same mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.