Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
US5827776A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 1997 |
| Grant date | Oct 27, 1998 |
| Priority date | — |
| Expiry date | Oct 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilevel interconnect structure is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels of conductors are staggered from each other in separate vertical and horizontal planes. A third conductor is advantageously spaced a lateral distance between at least a portion of two second conductors. The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.