Integrated circuit which uses a damascene process for producing staggered interconnect lines

US5846876A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Basab Bandyopadhyay · Austin, US
• H. Jim Fulford · Austin, US
• Robert Dawson · Austin, US
• Fred N. Hause · Austin, US
• Mark W. Michael · Cedar Park, US
• William S. Brennan · Austin, US

Key dates

• Filing date: Jun 5, 1996
• Grant date: Dec 8, 1998
• Expiry date: Jun 5, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.