Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
US5850105A · kind A · utility
261Cited by
3References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 21, 1997 |
| Grant date | Dec 15, 1998 |
| Priority date | — |
| Expiry date | Mar 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.