Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric

US5885877A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark I. Gardner · Mabank, US
• Robert Dawson · Austin, US
• H. Jim Fulford · Austin, US
• Frederick N. Hause · Austin, US
• Daniel Kadosh · Austin, US
• Mark W. Michael · Cedar Park, US
• Bradley T. Moore · Austin, US
• Derick J. Wristers · Austin, US

Key dates

• Filing date: Apr 21, 1997
• Grant date: Mar 23, 1999
• Expiry date: Apr 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/661
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A composite gate electrode layer incorporates a diffusion-retarding barrier layer disposed at the bottom of the gate electrode layer to reduce the amount of dopant which diffuses into the gate dielectric layer from the gate electrode layer. A lower nitrogen-containing gate electrode layer provides a diffusion-retarding barrier layer against dopant diffusion into the gate dielectric layer disposed therebelow, and an upper gate electrode layer is formed upon the lower layer and is doped to form a highly conductive layer. Together the first and second gate electrode layers form a composite gate electrode layer which incorporates a diffusion-retarding barrier layer adjacent to the underlying gate dielectric layer. The barrier layer may be formed by annealing a first polysilicon layer in a nitrogen-containing ambient, such as N.sub.2, NO, N.sub.2 O, and NH.sub.3, by implanting a nitrogen-containing material, such as elemental or molecular nitrogen, into a first polysilicon layer, and by in-situ depositing a nitrogen-doped first polysilicon layer. Diffusion of dopants into the gate dielectric layer may be retarded, as most dopant atoms are prevented from diffusing from the composite gate…