Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

US5899727A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Fred N. Hause · Austin, US
• Basab Bandyopadhyay · Austin, US
• H. Jim Fulford · Austin, US
• Robert Dawson · Austin, US
• Mark W. Michael · Cedar Park, US
• William S. Brennan · Austin, US

Key dates

• Filing date: May 2, 1996
• Grant date: May 4, 1999
• Expiry date: May 2, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa. A field dielectric, preferably oxide, is formed upon the field mesa and fills trenches between the field mesa and active mesas, leaving a substantially planar field dielectric commen…