Method for achieving global planarization by forming minimum mesas in large field areas

US5926713A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Fred N. Hause · Austin, US
• Basab Bandyopadhyay · Austin, US
• H. Jim Fulford · Austin, US
• Robert Dawson · Austin, US
• Mark W. Michael · Cedar Park, US
• William S. Brennan · Austin, US

Key dates

• Filing date: Sep 4, 1997
• Grant date: Jul 20, 1999
• Expiry date: Sep 4, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76229
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.