Method of making an integrated circuit with oxidizable trench liner

US5926717A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark W. Michael · Cedar Park, US
• Robert Dawson · Austin, US
• Basab Bandyopadhyay · Austin, US
• H. Jim Fulford · Austin, US
• Fred N. Hause · Austin, US
• William S. Brennan · Austin, US

Key dates

• Filing date: Dec 10, 1996
• Grant date: Jul 20, 1999
• Expiry date: Dec 10, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76227
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.