Shallow trench isolation formation with reduced polish stop thickness
US5930645A · kind A · utility
54Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76232
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.