Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
US5963803A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 1998 |
| Grant date | Oct 5, 1999 |
| Priority date | — |
| Expiry date | Feb 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.