Method of forming dual field isolation structures
US5966618A · kind A · utility
17Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 1998 |
| Grant date | Oct 12, 1999 |
| Priority date | — |
| Expiry date | Mar 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.