Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
US5998293A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1998 |
| Grant date | Dec 7, 1999 |
| Priority date | — |
| Expiry date | Apr 28, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodiz…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.