Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device

US6001713A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark T. Ramsbey · Sunnyvale, US
• Vei-Han Chan · San Jose, US
• Sameer Haddad · San Jose, US
• Chi Chang · Redwood City, US
• Yu Sun · Saratoga, US
• Raymond Yu · Irvine, US

Key dates

• Filing date: Sep 16, 1998
• Grant date: Dec 14, 1999
• Expiry date: Sep 16, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which coul…