Method of making NMOS and PMOS devices with reduced masking steps

US6060345A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Frederick N. Hause · Austin, US
• Robert Dawson · Austin, US
• H. Jim Fulford · Austin, US
• Mark I. Gardner · Mabank, US
• Mark W. Michael · Cedar Park, US
• Bradley T. Moore · Austin, US
• Derick J. Wristers · Austin, US

Key dates

• Filing date: Apr 21, 1997
• Grant date: May 9, 2000
• Expiry date: Apr 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain re…