Ion implantation into a gate electrode layer using an implant profile displacement layer

US6080629A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Mark I. Gardner · Mabank, US
• Robert Dawson · Austin, US
• H. Jim Fulford · Austin, US
• Frederick N. Hause · Austin, US
• Mark W. Michael · Cedar Park, US
• Bradley T. Moore · Austin, US
• Derick J. Wristers · Austin, US

Key dates

• Filing date: Apr 21, 1997
• Grant date: Jun 27, 2000
• Expiry date: Apr 21, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions. Each region may utilize separate displacement layer thicknesses, which allows dopants of different atomic mass to use similar implant energies. A higher implant energy may be used to dope a gate electrode layer which is much thinner than normal range statistics require, without implant penetration into und…