Shallow trench isolation with spacers for improved gate oxide quality

US6130467A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Basab Bandyopadhyay · Austin, US
• Nick Kepler · Saratoga, US
• Olov Karlsson · San Jose, US
• Larry Wang · San Jose, US
• Effiong Ibok · Sunnyvale, US
• Christopher F. Lyons · Fremont, US

Key dates

• Filing date: Dec 18, 1997
• Grant date: Oct 10, 2000
• Expiry date: Dec 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76224
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.