Semiconductor memory remapping
US6163490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 1999 |
| Grant date | Dec 19, 2000 |
| Priority date | — |
| Expiry date | Sep 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Defective memory is programmed to have a contiguous address space by dividing the logical address space of the memory into a plurality of address sections. The address section containing the address mapped to a defective memory location is identified. The physical memory locations originally mapped to the addresses in the identified address section are remapped to addresses in an address section at one end of the address space. The addresses in the end address section are disabled. Alternatively, spare memory is provided and the addresses in the end address section are remapped to physical locations in the spare memory. A similar remapping procedure is applied to repair defective data paths in a memory. The remapping procedure is applicable to memory devices or memory modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.