Shallow trench isolation formation without planarization mask

US6171962A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Olov Karlsson · San Jose, US
• Christopher F. Lyons · Fremont, US
• Basab Bandyopadhyay · Austin, US
• Nick Kepler · Saratoga, US
• Larry Wang · San Jose, US
• Effiong Ibok · Sunnyvale, US

Key dates

• Filing date: Dec 18, 1997
• Grant date: Jan 9, 2001
• Expiry date: Dec 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31053
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.