High selectivity oxide etch process for integrated circuit structures
US6171974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1992 |
| Grant date | Jan 9, 2001 |
| Priority date | — |
| Expiry date | Jan 24, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F2029/143
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A plasma etch process for oxide having high selectivity to silicon is disclosed comprising the use of a mixture of SiF.sub.4 and one or more other fluorine-containing etch gases in an etch chamber maintained within a pressure range of from about 1 milliTorr to about 200 milliTorr. Preferably, the etch chamber also contains an exposed silicon surface. The plasma may be generated by a capacitive discharge type plasma generator, if pressures of at least about 50 milliTorr are used, but preferably the plasma is generated by an electromagnetically coupled plasma generator. The high selectivity exhibited by the etch process of the invention permits use of an electromagnetically coupled plasma generator which, in turn, permits operation of the etch process at reduced pressures of preferably from about 1 milliTorr to about 30 milliTorr resulting in the etching of vertical sidewall openings in the oxide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.