Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same
US6198168A · kind A · utility
71Cited by
17References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Mar 6, 2001 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.