Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer
US6207577A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1999 |
| Grant date | Mar 27, 2001 |
| Priority date | — |
| Expiry date | Jan 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a self-aligned dual damascene structure in a semiconductor device arrangement forms an oxide dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A nitride etch stop layer is formed on the oxide dielectric layer, and a low k dielectric layer is formed on the nitride etch stop layer. A trench is etched into the low k dielectric layer, followed by the etching of a via into the oxide dielectric layer. The oxide dielectric material and low k dielectric material are selected so that they have different sensitivity to at least one etchant chemistry. Undercutting in the second dielectric layer caused by overetching is thereby prevented during the etching of the via in the second dielectric layer by employing an etch chemistry that etches only the oxide dielectric material and not the low k dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.