Semiconductor integrated circuit device, and method of manufacturing the same
US6215144A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1999 |
| Grant date | Apr 10, 2001 |
| Priority date | — |
| Expiry date | Jan 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta.sub.2 O.sub.5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.