Vertical fuse and method of fabrication
US6218279A · kind A · utility
20Cited by
1References
24Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Feb 24, 2000 |
| Grant date | Apr 17, 2001 |
| Priority date | — |
| Expiry date | Feb 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.