Dual barrier and conductor deposition in a dual damascene process for semiconductors
US6239021A · kind A · utility
32Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2000 |
| Grant date | May 29, 2001 |
| Priority date | — |
| Expiry date | Sep 5, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/915
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and a method for manufacturing therefor is provided in which a partial dual damascene deposition is performed to place a barrier, seed, and conductive layer in most of a via between two interconnect channels and then capping the via with a further barrier, seed, conductive layer to prevent electromigration between an interconnect channel and the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.