ROM-embedded-DRAM
US6243285A · kind A · utility
24Cited by
2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2000 |
| Grant date | Jun 5, 2001 |
| Priority date | — |
| Expiry date | Apr 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ROM is embedded within an array of DRAM cells by changing a single mask in a DRAM fabrication process to selectively short circuit the DRAM capacitor lower electrode to its own wordline to create a read-only "1" or to the wordline of an adjacent cell to create a read only "0".
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.