Semiconductor integrated circuit device and method of manufacturing the same
US6258649A · kind A · utility
56Cited by
3References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 3, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Sep 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to improve connection reliability of a feeding interconnection connected to an electrode of each of the information storage capacitive elements of a DRAM, the formation of a through hole for connecting the information storage capacitive element formed over each memory cell selection MISFET and a feeding interconnection is performed in a process different from that for the formation of a through hole for connecting an interconnection of a second wiring layer in a peripheral circuit, which is formed over the information storage capacitive element and an interconnection corresponding to a first wiring layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.