Dummy patterning for semiconductor manufacturing processes
US6259115A · kind A · utility
38Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 4, 1999 |
| Grant date | Jul 10, 2001 |
| Priority date | — |
| Expiry date | Mar 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76819
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for inserting dummy conductive channels along with the interconnected conductive channels. The dummy channels have an approximately even metal weight distribution to provide better plating uniformity, minimize CMP dishing, improve process heating uniformity, improve spin-on process properties, and increase etch and lithography uniformity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.