Multiple split gate semiconductor device and fabrication method

US6259142A · kind A · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Robert Dawson · Austin, US
• Mark I. Gardner · Mabank, US
• Frederick N. Hause · Austin, US
• H. Jim Fulford · Austin, US
• Mark W. Michael · Cedar Park, US
• Bradley T. Moore · Austin, US
• Derick J. Wristers · Austin, US

Key dates

• Filing date: Apr 7, 1998
• Grant date: Jul 10, 2001
• Expiry date: Apr 7, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/611

Abstract

A semiconductor integrated circuit having a multiple split gate is forming using a first polysilicon layer and a second polysilicon layer to form alternating first and second gate electrodes within an active area. The alternating gate electrodes are electrically isolated from one another by means of a gate insulating layer that is formed adjacent the side-walls of each firs gate electrode. Source and drain regions are formed adjacent the ends of the multiple split gate to define a channel region.