Method of improving MOS device performance by controlling degree of depletion in the gate electrode
US6274915A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 1999 |
| Grant date | Aug 14, 2001 |
| Priority date | — |
| Expiry date | Jan 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/235
Abstract
A design for an MOS transistor deliberately uses depletion in a polysilicon gate electrode to improve circuit performance. Conventional transistor design seeks to minimize depletion in a polysilicon gate electrode to increase drive current. According to an embodiment of the present invention, appropriate levels of depletion in the gate electrode, larger than conventional levels, simultaneously provide desired drive current while minimizing circuit delay. According to another aspect, circuit performance is improved by adjusting doping levels in the channel region to maintain a threshold voltage at the same level as that which is achieved with minimum depletion in a polysilicon gate electrode. A method of fabricating an MOS device including a polysilicon gate electrode with increased depletion is also provided. A self-aligned doping process is used in which the polysilicon gate, the source region, and the drain region, are simultaneously implanted to dopant concentrations of between 1.times.10.sup.19 and 5.times.10.sup.19 atoms/cm.sup.3.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.