Method to form smaller channel with CMOS device by isotropic etching of the gate materials
US6306715A · kind A · utility
27Cited by
13References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2001 |
| Grant date | Oct 23, 2001 |
| Priority date | — |
| Expiry date | Jan 8, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to form a MOS transistor with a narrow channel regions and a wide top (second) gate portion. A gate dielectic layer and a first gate layer are formed over a substrate. A second gate portion is formed over the first gate layer. Spacers are formed on the sidewalls of the second gate portion. In a critical step, we isotropically etch the first gate layer to undercut the second gate portion to form a first gate portion so that the first portion has a width less than the second gate portion. The spacers are removed. Lightly doped drains, sidewall spacers and source/drain regions are formed to complete the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.