Carrier and system for testing bumped semiconductor components
US6313651A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 1999 |
| Grant date | Nov 6, 2001 |
| Priority date | — |
| Expiry date | May 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.