Method for evaluating decoupling capacitor placement for VLSI chips
US6323050A · kind A · utility
11Cited by
5References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2000 |
| Grant date | Nov 27, 2001 |
| Priority date | — |
| Expiry date | Oct 2, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of evaluating decoupling capacitor placement for Very Large Scale Integrated Chips (VLSI) is disclosed. Included in the method is an analysis of the usage for each decoupling capacitor, the distance from the devices, and the locations of the devices and decoupling capacitors. Also addressed are the orientations and size of the components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.