Method for a short channel CMOS transistor with small overlay capacitance using in-situ doped spacers with a low dielectric constant
US6348385B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Nov 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.