Transmission lines for CMOS integrated circuits
US6373740B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Apr 16, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques. Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is then formed on the first layer of electrically conductive material. The method also includes forming a pair of electrically conductive lines on the first layer of insulating material. Moreover, a transmission line is also formed on the first layer of insulating material. In particular, the transmission line is formed between and parallel with the pair of electrically conductive lines. The method also includes forming a second layer of insulating material on both the transmission line and the pair of electrically conductive lines. A second layer of elect…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.