Package for stacked integrated circuits
US6414396B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Jul 2, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18165
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of integrated circuit packages for housing a plurality of integrated circuits are disclosed, along with methods of making the packages. One integrated circuit package comprises a substrate having a first surface having first metallizations thereon, an opposite second surface, and a plurality of apertures between the first and second surfaces. A first integrated circuit having a first surface with first bond pads thereon and an opposite second surface is mounted on the second surface of the substrate so that the first bond pads are superimposed with an aperture. Each first bond pad is electrically connected by a first bond wire extending through the superimposing aperture to a first metallization. A second integrated circuit having a first surface with conductive second bond pads thereon is mounted on the second surface of the first integrated circuit. In particular, the first surface of the second integrated circuit is placed on the second surface of the first integrated circuit so that the second bond pads are superimposed with one or more of the apertures through the substrate. Each second bond pad is electrically connected by a second bond wire extending through the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.