Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge

US6417056B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Elgin Quek · Singapore, SG
• Ravi Sundaresan · San Jose, US
• Yang Pan · Singapore, SG
• James Yong Meng Lee · Singapore, SG
• Ying-Keung Leung · Hong Kong, CN
• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Lap Chan · San Francisco, US

Key dates

• Filing date: Oct 18, 2001
• Grant date: Jul 9, 2002
• Expiry date: Oct 18, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017

Abstract

A method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant is described. A gate electrode is provided overlying a gate dielectric layer on a substrate and having a hard mask layer thereover. An oxide layer is formed overlying the substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are implanted. Second spacers are formed on the first spacers. Source/drain regions are implanted. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers and underlying oxide layer are removed. The exposed substrate underlying the second spacers is etched into to form a microtrench undercutting the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The microtrench reduces the effective dielectric constant at the overlap between th…