Calibration target for calibrating semiconductor wafer test systems
US6420892B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2000 |
| Grant date | Jul 16, 2002 |
| Priority date | — |
| Expiry date | Oct 10, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49197
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A calibration target for calibrating semiconductor wafer test systems including probe testers and probe card analyzers is provided. Also provided are calibration methods using the calibration target, and a method for fabricating the calibration target. The calibration target includes a substrate with various three dimensional alignment features formed thereon. A first type of alignment feature includes a contrast layer and an alignment fiducial formed on a tip portion thereof. The contrast layer and alignment fiducial are configured for viewing by a viewing device of the probe card analyzer, or the test system, to achieve X-direction and Y-direction calibration. A second type of alignment feature includes a conductive layer formed on a tip portion thereof, which is configured to electrically engage a contact on a check plate of the probe card analyzer, or a probe contact on a probe card of the test system, to achieve Z-direction calibration. The alignment features can be formed by forming raised members on a silicon substrate, and depositing and etching metal layers on the raised members.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.