Semiconductor device having a porous buffer layer for semiconductor device
US6433440B1 · kind B1 · utility
12Cited by
13References
19Claims
0Family size
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Key dates
| Filing date | Jun 5, 1998 |
| Grant date | Aug 13, 2002 |
| Priority date | — |
| Expiry date | Jun 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor device having a three-layered buffer layer comprising core layer 1 having interconnected foams such as a three-dimensional reticular structure and adhesive layers 2 provided on both sides of the core layer as a stress buffer layer between semiconductor chip 5 and wiring 4 to lessen a thermal stress generated between the semiconductor device and the package substrate, where a thickness ratio of core layer 1 to total buffer layer is at least 0.2, the production process can be simplified by using such a buffer layer, thereby improving the mass production capacity and enhancing the package reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.