Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation

US6436770B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Ying-Keung Leung · Hong Kong, CN
• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Lap Chan · San Francisco, US
• Elgin Quek · Singapore, SG
• Ravi Sundaresan · San Jose, US
• Yang Pan · Singapore, SG
• James Yong Meng Lee · Singapore, SG

Key dates

• Filing date: Nov 27, 2000
• Grant date: Aug 20, 2002
• Expiry date: Apr 6, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/512

Abstract

A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Con…