Thin film wiring scheme utilizing inter-chip site surface wiring
US6444919B1 · kind B1 · utility
16Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/467
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.