Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material
US6451641B1 · kind B1 · utility
110Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for fabricating a semiconductor device, including providing a semiconductor substrate; depositing on the semiconductor substrate a layer of a high-K gate dielectric material; depositing on the gate dielectric material layer a polysilicon or polysilicon-germanium gate electrode layer, in which the step of depositing the polysilicon or polysilicon-germanium gate electrode layer includes providing non-reducing conditions in a CVD apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.