Feedback method to optimize electric field during channel erase of flash memory devices
US6452840B1 · kind B1 · utility
25Cited by
7References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2000 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3472
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of erasing a flash memory device that improves reliability and reduces the decrease in erase speed. The state of erasure is determined either during an erase phase or a verify phase and the information is fedback to a controller that adjusts the erase vertical electrical field that is to be applied to the array. The vertical electrical field is adjusted by changing the gate voltage, the well voltage or changing both simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.