Higher program VT and faster programming rates based on improved erase methods
US6456533B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2001 |
| Grant date | Sep 24, 2002 |
| Priority date | — |
| Expiry date | Feb 28, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.