Method to form a self-aligned CMOS inverter using vertical device integration

US6461900B1 · kind B1 · utility

Assignee

• Chartered Semiconductor Manufacturing LTD · SG

Inventors

• Ravi Sundaresan · San Jose, US
• Yang Pan · Singapore, SG
• James Lee Yong Meng · Singapore, SG
• Ying-Keung Leung · Hong Kong, CN
• Yelehanka Ramachandramurthy Pradeep · Singapore, SG
• Jia Zhen Zheng · Singapore, SG
• Lap Chan · San Francisco, US
• Elgin Quek · Singapore, SG

Key dates

• Filing date: Oct 18, 2001
• Grant date: Oct 8, 2002
• Expiry date: Oct 18, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS…